The challenges associated with device scaling or reducing the size of device geometries have become a focus of attention for both bipolar and MOS VLSI technologies in recent years. In addition, the integration of FET structures and bipolar transistors on a single substrate has become very desirable. Each of these technologies provides inherent advantages. Bipolar transistors provide high transconductance and, as a result, are very suitable for high speed VLSI devices. On the other hand, CMOS technology offers the advantages of low power operation and very high packing density. It has become clear that the exploitation of the high current driving capabilities of the bipolar transistor is important and that bipolar device scaling is critical to obtaining even higher levels of bipolar or merged bipolar CMOS integration.
Previous efforts to scale the geometries of the bipolar transistor have been directed to reducing the lateral dimensions of the device by photolithographically scaling the feature sizes. Using this approach, the desired breakdown voltages are typically accomplished by maintaining critical lateral spacings through appropriate adjustments in photomask pattern dimensions. By incorporating processes that include the use of polysilicon and self-alignment techniques, even further advances in performance and packing density have been realized. These improvements are largely the result of minimizing excessive parasitic extrinsic regions of the bipolar device. One recent technique to reduce the collector-base area is to self-align the emitter to the base by making direct contact to the emitter with a polysilicon layer. Polysilicon has also been used to contact the base of the transistor which has the effect of reducing the collector to base area. See, for example, Cuthbertson et al, Self-Aligned Transistors with Polysilicon Emitters for Bipolar VLSI, IEEE Trans. Electron Devices, vol. ED-32, No. 2, pp. 242-247., Feb. 1985.
Such techniques have more recently been implemented in a bipolar-based BICMOS process which uses the second level polysilicon layer of the CMOS process to form the bipolar polysilicon emitter. This allows a small sized, shallow emitter structure without additional processing steps (see Ikeda et al, High-Speed BICMOS Technology with a Buried Twin Well Structure, IEEE Trans. Electron Devices, vol. ED-34, No. 6, pp. 1304-1309, June 1987).
Other processes for producing multilayer bipolar and MOS structures having reduced packing density have incorporated the use of vertical or sidewall insulating layers. See for example J. Riseman U.S. Pat. No. 4,234,362, issued Nov. 18, 1980 or V. L. Rideout U.S. Pat. No. 4,085,498, issued Apr. 25, 1978.
While the above described methods have allowed ever increasing improvement in device performance and packing density, there exists a need for even further reduction in feature size that is not limited by photolithography for controlling critical dimensions between diffusions. In addition, there exists a need for improving device performance by eliminating parasitic peripheral diode effects and the level of stored charge in the collector region. Finally, it would be desirable to provide a method of producing a scaled bipolar device having the above improvements with a simplified manufacturing process that is compatible with various bulk and silicon-on-insulator isolation schemes as well as CMOS process technology.
It is therefore an object of the invention to provide a method of making a bipolar transistor that reduces the area of the transistor structure and improves the packing density of integrated circuits incorporating said transistor. It is also an object of the invention to provide a bipolar transistor having a reduced extrinsic base area with a corresponding reduction in the parasitic capacitance to improve device switching performance. It is yet another object of the present invention to provide a simplified bipolar transistor process which eliminates the need for a highly doped buried collector layer. It is still another object of the invention to provide a bipolar transistor process which improves voltage breakdown control by device scaling which is independent of photolithographic operations. An additional object of the invention is to provide a bipolar transistor that reduces the effect of parasitic emitter to base diode characteristics. Finally, it is a further object of the present invention to provide a bipolar transistor process that is (automated) layout compatible with CMOS manufacturing processes.